The present invention relates to an analog front-end circuit, an electronic instrument, and the like.
An image sensor (e.g., CCD or CMOS sensor) used for electronic instruments (e.g., image reader) is configured so that an analog image signal relating to a document or the like read by the image sensor is converted into a digital image data using an A/D converter. JP-A-2004-297146 discloses technology relating to an analog front-end circuit (image processor) having an A/D converter.
The analog image signal output from the image sensor contains a DC offset component. The voltage level of the image signal may exceed the input allowable range of the analog front-end circuit due to the DC offset component. Therefore, in order to remove the DC offset component to set the voltage level of the image signal at an appropriate level, it is desirable to provide an AC coupling capacitor between the output of the image sensor and the input of the analog front-end circuit and provide a clamp circuit in the analog front-end circuit.
The clamp operation of the clamp circuit is classified into a bit clamp operation and a line clamp operation. The bit clamp operation is used for correlated double sampling and the like. The bit clamp operation is not suitable for applications which require high-speed A/D conversion. The line clamp operation is suitable for applications (e.g., office instruments) which require high-speed A/D conversion. However, when an error of a black level drawn toward a clamp level has occurred, accurate A/D conversion cannot be implemented when a sudden change in density of a document or the like has occurred.